Fundamentals of IC processing. Transistor based logic design using gates and switches, nMOS, CMOS, GaAs MESFET, BiCMOS logic design. Combinatoric arrays, sequential design, memory architectures, design for testability and observability. VLSI design using FPGAs.
Students who pass this course will be able to:
Withdrawal dates and process:
There are two lectures each week.
Tutorials will be held most weeks to review assessment material, reinforce lecture content and answer specific student queries. The first four or five tutorial sessions will cover the VHDL design and several of these may be practical tutorials held in the lab. You should review the Tutorial material BEFORE attending the labs.
The course includes nine 3-hour assigned laboratory experiments. Four hours are assigned to each laboratory session to cater for students who have to miss an hour because of a lecture clash.
Student feedback on University courses may be found at: www.cad.vuw.ac.nz/feedback/feedback_display.php
Laboratory sessions will be scheduled in the first week of term and will commence in the second week. The laboratory sessions will be held in CO239.
Students will be provided with a comprehensive study guide which contains lecture slides but with blanks that will need to be filled-in during the lectures. A complete PDF file of these slides is available via BlackBoard for students who have either missed the lecture or wish to have the material entered in advance. The study-guide also includes sections of full notes. These sections have been included for those topics that are not well covered by the available text books. Additional material will be handed out in class and made available electronically.
A laboratory manual with the laboratory exercises and VHDL tutorial is also provided.
The following texts contain information that would be useful to assist you in following the lecture material:
In addition to achieving an overall pass mark of at least 50%, students must:
If you believe that exceptional circumstances may prevent you from meeting the mandatory course requirements, contact the Course Coordinator for advice as soon as possible.
This course has two one hour tests that will contribute 50% of the final grade. The internal course assessment comprises 15% written assignments, 10% mini-tests and 25% laboratory work, detailed below
|Assessment Item||Due Date or Test Date||CLO(s)||Percentage|
|internal tests||Week 8 and 12||CLO: 1,2,3,4||50%|
|closed book mini-tests administered during lecture time||fortnightly||CLO: 1,2,3,4||10%|
|three internal written assignments||CLO: 1,2,3,4||15%|
|laboratory work including laboratory write-ups and mini project||CLO: 1,2,3,4||25%|
Late assessment is penalised at a rate of 5% per day the assessment is late.
Individual extensions will only be granted in exceptional personal circumstances, and should be negotiated with the course coordinator before the deadline whenever possible. Documentation (eg, medical certificate) may be required.
Lab work is submitted through the ECS submission system, accessible through the course web pages. Marks and comments will be returned through the ECS marking system, also available through the course web pages.
You are required to submit a formal laboratory report for each of the assigned labs. These should be of professional standard detailing the objective of the laboratory exercise, the methodology employed, justification for any design decisions, results obtained and an analysis or evaluation of your results. You should answer any questions asked of you in the laboratory manual.
Note, there is a non-linear relationship between the write-up mark and your overall laboratory grade. For example, a mark of 8/10 for a write-up certainly does not guarantee you an A grade for the laboratory work since several of these lab assessments are designated as mastery assessment items. This will be further explained in the lectures.
We encourage you to discuss the principles of the course and assignments with other students, to help and seek help with programming details, problems involving the lab machines. However, any work you hand in must be your own work.
The expectation is that you will do roughly 10 hours of work per week on average. This will normally comprise 2 hours of lectures, 1 hour tutorial, 3 – 4 hours of laboratory work, and an average of 3 – 4 hours of assignment work, laboratory write-ups, and background reading.
The following material is expected to be covered during the lectures, although the exact order is expected to change with additional lectures being planned on FPGA design techniques. An approximate lecture schedule (excluding these changes) is as follows:
|Lecture||FETS and Logic I
|Lecture||FETS and Logic II
FET operation, logic gate construction
|Lecture||FETS and Logic III
nMOS and CMOS logic gates
Introduction to FPGA
Testbench design and IP block design
|Lecture||Electrical Properties of nMOS I
nMOS current equations
|Lecture||Electrical Properties of nMOS II
nMOS ratio calculations, nMOS parameters
|Lecture||Electrical Properties of CMOS I
CMOS regions and behaviour
|Lecture||Electrical Properties of CMOS II
CMOS and BiCMOS parameters
|Lecture||CMOS & nMOS Design I
|Lecture||CMOS & nMOS Design II
Design rules and memory
Covers lectures 1 - 12 inclusive
|Lecture||Basic Circuit Concepts I
Sheet resistance, capacitance
|Lecture||Basic Circuit Concepts II
|Lecture||VLSI Design Considerations I
Gate vs switch logic, design issues
|Lecture||VLSI Design Considerations II
Packaging and power dissipation
|Lecture||Reliability and Testing I
Reliability measures, testing techniques
|Lecture||Reliability and Testing II
Testing techniques, design for testability
High level design
High speed design
|Test|| TEST 2
Covers lectures 12 – 24 inclusive
Any additional information regarding this course will be posted on blackboard.
Offering CRN: 18513
Prerequisites: ECEN 202 (or PHYS 234), ECEN 204
Duration: 08 July 2019 - 10 November 2019
Starts: Trimester 2